This invention relates to a reset signal generating circuit for generating a reset signal during turning on a power supply. More particularly, the invention is concerned with a reset signal generating circuit which is adapted to reduce consumption of electric power by a reset circuit during operating a system circuit, and generate a reset signal without fail regardless of a rising characteristic in power supply voltage during resetting the system circuit.
Conventionally, there have been reset signal generating circuits for resetting a system circuit during turning on a power supply, as shown in FIG. 4(a) and FIG. 4(b).
The circuit of FIG. 4(a) is a reset signal generating circuit that uses a CR time constant circuit adapted to supply to an output terminal R.sub.OUT a low level signal lower than a power supply voltage V.sub.cc for a time period determined by the on-resistance R of a transistor Q5 and the capacitance of a capacitor C5. That is, the transistor Q5 formed for example by a PMOSFET and the capacitor C5 are connected in series between a terminal of power supply V.sub.cc and a ground GND. While the capacitor C5 is being charged after turning on the transistor Q5, a low level signal lower in voltage than a power supply voltage V.sub.cc is outputted through the output terminal R.sub.OUT. Here, the transistor Q5 has a gate connected to the ground GND.
This circuit utilizes the on-resistance of the active-element transistor Q5 as a resistance instead of a passive-element resistance. Consequently, the transistor Q5 will not be turned on until the gate-to-source voltage of the transistor Q5 is raised to a threshold voltage. Here, the threshold voltage means a minimum voltage for turning on a transistor that is applied between the gate and the source of the transistor. As a result, the charging electricity to the capacitor C5 is not started until the threshold voltage of the transistor is reached, even where the slant of rising in the power supply voltage V.sub.cc is smaller than the slant of electricity charging given by the CR time constant, ensuring time period for voltage lower than the power supply voltage V.sub.cc.
The circuit shown in FIG. 4(b) includes voltage-divisional resistances R5, R6 connected in series between a power supply voltage V.sub.cc terminal and a ground GND, and a comparator COM connected to a connection point between these resistances. The divisional voltage V.sub.R6 taken out of the connection point is compared with a constant voltage V.sub.C by the comparator COM. The comparator COM outputs a low level signal as a reset signal to an output terminal R.sub.OUT, before the power supply voltage V.sub.cc becomes to such a level that the divisional voltage V.sub.R6 is higher than the constant voltage V.sub.C.
In the circuit of FIG. 4(a), however, the gate of the transistor Q5 is fixedly connected to the ground GND. Consequently, even after the power supply voltage V.sub.cc is turned off and becomes a zero voltage, there remains a potential corresponding to the threshold voltage V.sub.th of the transistor Q5. To this end, the capacitor C5 is not completely discharged and the potential on the output terminal R.sub.OUT is not to be reduced down to a zero voltage. As a result, where performing resetting by once turning off the power supply, there are cases that no reset signal be available on the output terminal R.sub.OUT.
Meanwhile, in the circuit of FIG. 4(b), if the power supply voltage V.sub.cc is abrupt in rising, there encounters a case that the time period for generating a reset signal to the output terminal R.sub.OUT is too brief to stably performing a reset operation. Further, this circuit has an electric current steadily flowing through the resistances R5, R6 connected between the power supply voltage V.sub.cc terminal and the ground GND. There is a problem that it is inconvenient for use in an integrated circuit for portable electric appliances and devices because of relatively high electric power consumption.